The object of the invention is an improved method and circuit arrangement for processing a signal. The invention can preferably be used in processing analog signals in embodiments where it is essential to achieve small energy consumption. By the term signal processing one means, in this context, for example, the summing, difference, integration and differentiation of voltage representing a signal, or charge or current equally well.
The processing of analog signals is often connected with the problem of how to achieve small energy consumption since continuous current consumption of linearly operating active analog circuits such as, for example, operational amplifiers, is extremely high.
Basic methods are prior known in which signal samples can be processed, substituting for structures which consume continuously current, by processing a signal by means of a switching transistor transferring exclusively charge impulses. Methods of this kind have been described in patent specifications Fl 89838 (corresponds to specifications EP 473436 and U.S. Pat. No. 5,387,874) and FI 931831 (corresponds to specifications EP 621 550 and U.S. Pat. No. 5,497,116).
In U.S. Pat. No. 5,387,874, an integrating circuit has been described wherein storing of sample charges taken from signal voltage to a sampling capacitor and further discharge of sample charges from the sampling capacitor to an integrating capacitor are controlled by means of switches. A similar arrangement can also be used for implementing signal processing elements other than the integrator. The described circuit consumes current essentially only when charges are being transferred. One disadvantage of such an arrangement is, however, that for the positive and negative cycles of the signal voltage, one requires separate switching arrangements and separate clock phases controlling the switches, and this complicates the circuit. In addition, the use of separate circuit parts for processing the negative and the positive cycle of a signal may cause signal distortions due to threshold voltages and differences between the components.
Disadvantages of the above mentioned circuit can be avoided by using the solution described in U.S. Pat. No. 5,497,116. In the following, the operation of the circuit arrangement presented in the specification concerned is described in greater detail to make it easier to understand the operation and advantages of the present invention compared to the prior art.
FIG. 1 shows a signal processing circuit which has been implemented by means of transistors T1 and T2 and in which there is a time discrete integral of the voltage (U.sub.S -U.sub.Ref) as a final result. An MOS transistor of an N type, i.e. an N-MOS transistor has been used as transistors T1, T2. Switches S.sub.21 -S.sub.30 of the circuit shown in FIG. 1 are controlled by clock signals 1-4. The clock signals 1-4 control the switches in four successive phases so that, for example, during the clock cycle1, the clock signal controls those switches into a conducting state which are controlled by the clock signal 1. In the following, the switches are indicated by means of the letter S and indexes so that the subindex refers to the number of the switch which is numbered consecutively, and the superscript refers to those clock phases during which the switch is in a conducting state. For example, the indication S.sub.21.sup.1,3 indicates that the switch 21 is in a conducting state during clock phases 1 and 3 and is controlled by clock signals 1 and 3. During the other clock phases, 2 and 4, said switch is in a non-conducting state. Correspondingly, the voltage indication described with a superscript indicates voltage which is present during the clock phase indicated by the superscript, and the charge indication equipped with a superscript indicates charge which is present or is being transferred during the clock phase indicated by the superscript. Accordingly, for example, U.sub.Ci.sup.2 indicates the voltage U of the capacitance C.sub.i during/at the end of the clock phase 2. Clock pulses are so-called non-overlapping clock pulses which means that during a certain phase, only the switches which are meant to be closed during that phase are in a conducting state and the other switches are open.
The operation of clock phases 1-4 of the connection is shown in detail in FIGS. 2-5 in which only the necessary elements with respect to the operation of each clock phase are presented for the circuit according to FIG. 1. The signs (polarity, e.g. positive or negative) of signals and voltages are indicated in relation with the ground potential.
FIG. 2 shows the operation during clock phase 1. For the clock phase 1, switches S.sub.21, S.sub.22, S.sub.23 and S.sub.24 are closed, during which a charge transferring capacitor C.sub.i, which herein is also called a sampling capacitor C.sub.i, is charged to a voltage U.sub.Ci.sup.1 : EQU U.sub.Ci.sup.1 =U.sub.S.sup.1 +U.sub.Ref +U.sub.th1 ( 1)
in which U.sub.th1 is a threshold voltage of the gate/source voltage of a transistor T1. When the gain of the transistor T1 is great, the charge being transferred to the sampling capacitor C.sub.i is taken essentially from the supply voltage VDD of the circuit and not from the signal voltage U.sub.S.
The operation in the subsequent clock phase 2 is illustrated in FIG. 3. During the clock phase 2, switches S.sub.26, S.sub.27 and S.sub.28 are in a conducting state (closed) during which a sampling capacitor C.sub.i forms a gate/source voltage to a transistor T2 enabling current flow from the positive supply voltage VDD to an integrating capacitor C.sub.O. The current flow continues until the sampling capacitor C.sub.i has become discharged to a threshold voltage U.sub.th2 of the gate/source junction of the transistor T2 at which time the current flow stops. Thus charge becomes transferred from the sampling capacitor C.sub.i to the integrating capacitor C.sub.O until the voltage of the capacitor C.sub.i has reduced to the value U.sub.th2. Then, during the clock phase 2, a charge EQU .DELTA.Q.sup.2 =C.sub.i (U.sub.S +U.sub.Ref -U.sub.th1 -U.sub.th2) (2)
has become transferred from the charge transferring capacitor C.sub.i to the integrating capacitor C.sub.O.
FIG. 4 illustrates the operation of the circuit during clock phase 3 when the switches S.sub.21, S.sub.23, S.sub.24 and S.sub.25 are closed. Then the sampling capacitor C.sub.i is connected via the transistor T1 to the reference voltage U.sub.ref at which the capacitor is charged to the voltage EQU U.sub.Ci.sup.3 =U.sub.Ref -U.sub.th1 ( 3)
FIG. 5 illustrates the operation of the circuit during the final clock phase 4 when the switches S.sub.26, S.sub.29 and S.sub.30 are closed. Then the sampling capacitor C.sub.i forms a gate/source voltage to the transistor T2 enabling current flow through the sampling capacitor C.sub.i from the integrating capacitor C.sub.O to a lower supply voltage VSS. Current flow continues until the sampling capacitor C.sub.i has become discharged to a threshold voltage U.sub.th2 of the gate/source junction of the transistor T2. Then, the amount of negative charge which has become transferred to the integrating capacitor C.sub.O equals: EQU .DELTA.Q.sup.4 =-C.sub.i (U.sub.Ref -U.sub.th1 -U.sub.th2) (4)
When the gain of the transistor T2 is high, as is the case when a good quality bipolar transistor is concerned, or almost infinite such as the gain of a field-effect transistor (for example, an MOS transistor), also in transfer phases of a charge, the transferring charge taken from the supply voltage (VDD, VSS) is essentially as high as required for the transfer of a desired charge from a sampling capacitance C.sub.i to an integrating capacitance C.sub.O. During all clock phases 1-4, the charge having become transferred to the output of the connection which is taken from the integrating capacitor C.sub.O, is the sum of the equations (2) and (4), in other words EQU .DELTA.Q.sub.tot =C.sub.i (U.sub.S +U.sub.Ref -U.sub.Ref)=C.sub.i U.sub.S ( 5)
Correspondingly, during one repetition phase Tr of the clock phases, that is, during clock phases 1-4, the voltage of the integrating capacitor C.sub.O changes its value by the amount indicated by the equation (6): ##EQU1##
Thus, from a connection according to FIG. 1, a discrete time, positive integrating connection of a signal voltage is formed, and the weighting coefficient of its time integration is C.sub.i /C.sub.O. The sign of the integration can be changed to negative by changing the execution order of the above described clock phases 2 and 4 with each other, in which case the operation performed during clock phase 4 is carried out after phase 1 and the operation during clock phase 2 is performed after phase 3. In this case, also the signs of the above described equations (2) and (4) and thus also the signs of the equations (5) and (6) become changed (positive changes to negative and negative changes to positive). Based on this connection, many variations can easily be achieved according to what kind of transistors are used (NPN, PNP, N-MOS or P-MOS) and according to whether one wishes to implement the connection using only one transistor instead of two transistors (above T1 and T2).
The above presented solution according to the prior art leads to the result that after the charge has become transferred, the circuit is essentially currentless and the dependence on threshold voltages and non-linearities of circuit elements is minimal. When one implements a circuit according to the solution by CMOS transistors, the circuit has, however, three fundamental limitations. Firstly, a part of switching transistors are floating with voltages which are being processed, which leads in implementations to changes in a threshold voltage due to a so-called backgate phenomenon. This can be revealed as non-linearity in the operation of the circuit in such a way that when taking a sample and transferring a sample, the transistor may have different threshold voltages. In addition, with unequal signals, threshold voltages have values which differ from each other. Typically a transistor would float in an area of approximately one volt in which case the threshold voltage could fluctuate by some millivolts. That is the reason why it would be preferable to minimize potential fluctuations of the transistor when the implementation of the method is considered.
Secondly, in circuits according to prior known solutions a transistor becomes transferred to a currentless state so that the voltage of a gate falls to a threshold voltage. This occurs slowly since the gate voltage V.sub.GS of the transistor is modified by the charging of the capacitance C.sub.i and this charging again happens only through channel resistance which at the same time increases to approach an infinite value. Thus the switching may be slow and the increase in channel resistance also causes noise. However, in the implementation based on a bipolar transistor, said speed and noise properties are improved.
The third limitation connected to the prior art is that the implementation of more than two (for example, four) clock signals in different phases complicates the circuit. Particularly in implementations which are integrated for silicon, the wiring of four clock signals in different phases demands a considerably greater area than that required for wiring of two clock phases, although the number of switches would not be significantly high. Thus it is preferable to strive to reduce the number of clock signals needed in different phases.